As fine pitch 3D wafer-level packaging becomes increasingly popular, wafer-level prebond testing of various interconnect structures has become an important challenge. Moreover, improving the current-carrying capacity (CCC) of probes and minimizing damage to the probes and micro-interconnect structures are also critical issues. Formfactor offers a range of MEMS, solder bump vertical probe cards to address these challenges. These cards offer high parallelism, stable contact resistance and superior contact precision for wafer-level probing.
Material
Solder
Bump Vertical Probe Cards are designed to probe a broad range of materials
including aluminum pads and copper bumps. These probes are based on a proven
Vertical Contact Technology (VCT) technology that offers stable contact
resistance, high parallelism and superior contact precision for multi-die and
full array testing.
As
3D wafer-level packaging becomes more common in semiconductor industries, the
test system manufacturers have been challenged to improve current-carrying
capacity (CCC) and minimize damage to the probe and various interconnect structures
such as a solder ball, Cu pillar microbump and TSV structure.
As
a result, a new microelectromechanical (MEMS) design of a solder bump vertical
probe cards was proposed to reduce electrical resistivity and high contact
stress to minimize the damage to the probe and various interconnect structures.
The proposed Au-NiCo MEMS vertical probe was based on the NiCo probe and
applied gold (Au) material inside and outside the NiCo probe. The new design
offered a better probing efficiency and higher test yield than the conventional
NiCo probe.
Tip Shape
A
solder bump vertical probe cards comprises a multi-layer ceramic substrate 32 and a number
of perpendicularly aligned vertical probes 321 on the bottom surface of the
substrate. The tips of the probes contact solder bumps 22 provided on the I/O
terminals 21 of an integrated circuit 20 to be tested.
The
tip shape of the vertical probes most preferably depresses the near central
upper portion of the solder bumps 22. This enables appropriate plastic
deformation of the solder bumps 22 to adapt to the disposition of the probes
321 and to prevent them from being misaligned with respect to the solder bumps
22.
Optimal
contact force during wafer level burn-in (WLBI) is critical to ensure a
die-level test that does not damage the interlayer dielectric (ILD) under the
solder bumps on a wirebond package or flip chip die. Several factors influence
WLBI, including the length of the probe over-travel distance; scrub; contact
friction coefficient; and the probe tip shape.
Guide Plate
The
guide plate of Solder Bump Vertical Probe Cards is a critical component for the
overall probing efficiency, reliability, and post fabrication process of these
probes. Deformation of the guide plate or interconnect structures during probe
contact is a significant concern.
The
Guide Plate of a solder bump vertical probe cards is designed to allow relative
movement of the wiring structure 120 with respect to the guide plate 140 and
the DUT 116 as well as to allow for thermal expansion or contraction of both
the wiring structure 120 and the guide plate 140. This can be due to the
relative temperature of the guide plate 140 and the DUT 115 or a thermal
gradient across the wiring structure and the DUT 116, as discussed in the next
section.
To
compensate for this relative movement of the wiring structure and guide plate,
each probe 150 is secured in one of the probe guides 146 in the guide plate and
compliantly connected to one of the electrical contacts 130 on the first side
124 of the wiring structure 120. Moreover, the flexure element 332, body 312,
and compliant connection portion 304 of each probe 150 extend in a plane
substantially parallel to the plane of the electrical contacts.
Space Transformer
While
solder bump vertical probe cards use wired space transformers (WST) to route electrical
contacts on the telescopic "spring pins" or solder bumps, advanced
technology solutions are rapidly emerging. These solutions are designed to
increase the number of electrical contacts per unit of area (m2) and/or reduce
the minimum pitch.
However,
these technologies are expensive and difficult to produce. These solutions can
also have non-recurring engineering charges that result in delays for new
product introductions. This problem is particularly severe for wafer level chip
scale packages (WLCSP). WLCSP rely on probe cards to bring up and debug silicon
designs that have been developed on development wafers.
As
a result, these devices require high NRE charges for probe card production. In
addition, these probe cards have to be built in advance and fabricated quickly.
This
can cause a significant delay to the delivery of probe cards for new device
designs. Typically, delivery times for new MLCs and MLOs can be on the order of
ten to twelve weeks.